ClockDivider

Overview

Simple clock divider in Verilog. It divides the signal of the clock (i.e. decreases the signal) by 2, 4, 8, and 16 times. Made using the book "Designing Video Game Hardware in Verilog" Open-source project by Gabriel Lopez, published on GitHub.

Highlights

• 1 star on GitHub
• 1 fork
• Primary language: Verilog
• Open source — view the code and contribute on GitHub

Built with

• Verilog