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Neowizen

Data / ML Engineer

// puerto rico, pr · UTC-4

Computer Science and Software engineering student at RUM in Puerto Rico. Passionate about scien…

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profile sourced from GitHub

Scouting report

FPGA / digital-design engineer who finishes what he starts

assessed from open-source footprint

Mid
73signal

Yamil is a hardware-leaning CS student with a rare 0% abandonment rate and near-perfect consistency (98): his '4-Bit ALU Designs' spans a discrete 74HC-series PCB with exhaustive firmware validation plus a synthesized FPGA build in Verilog. His most-starred work, Zypher (5★), is a polished Python/yt-dlp downloader. Low-level systems and FPGA roles are the real fit; web/product polish is not his focus yet.

Authorship & open source

Solo authorwrote 100% of commits on 4-Bit-ALU-Designs
6 merged PRs105 commits / yr3 external projects

Contributes to

  • Uznavi/Perfect-Racer1
  • JimCaraballo/ControllerToEsp320
  • iancarlo049/Memory-Game0

What they build

Systems42%
Backend29%
Data / ML29%

Industry experience

  • IoT & Hardware
  • Gaming
  • Media & Streaming

Signal breakdown

Originality89
Impact64
Consistency100
Polish37
Stars

10

top repo 5

Original repos

13

0% forks

Followers

9

On GitHub

2.8 yr

Live demos

0

Activity

Active

0% stale

Strengths

  • Verified author — wrote 100% of commits on 4-Bit-ALU-Designs
  • Open-source contributor — 3 external projects incl. Uznavi/Perfect-Racer (1★)
  • Original builder — 13 of their own repositories
  • Consistently active, low abandonment
  • Systems focus with Backend
  • Domain experience in IoT & Hardware & Gaming
  • Core stack: Python, Assembly, C++, Verilog

About

Computer Science and Software engineering student at RUM in Puerto Rico. Passionate about science, robotics, hardware and software. — 13 public repositories and 9 followers on GitHub.

Skills

  • Python
  • Assembly
  • Verilog
  • C++
  • Digital Design
  • Fpga
  • Hardware
  • Tang Nano 9k

Featured work