Scouting report
UPR-Mayaguez computer-engineering student, strong hardware coursework
assessed from open-source footprint
An undergraduate computer-engineering student at UPR-Mayaguez whose repos center on low-level and hardware topics — a RISC pipelined microprocessor and CPU/RAM design in Verilog, plus Java game and data-structures projects from advanced-programming courses. The work is clearly academic (dated to specific class terms), with no stars, deployments, or verified external contributions, and the account is currently dormant. The genuine strength is unusual-for-this-set exposure to computer architecture and Verilog; the limit is that it's coursework rather than maintained or independent work.
Authorship & open source
What they build
Signal breakdown
0
9
18% forks
2
8.5 yr
0
Quiet
100% stale
Strengths
- Verified author — wrote 100% of commits on RISC-Pipelined-CPU-RAM
- Original builder — 9 of their own repositories
- Backend focus with Mobile
- Core stack: Java, Verilog, JavaScript, Lex
About
Skills
- Java
- Verilog
- Arm
- Computer Architecture
- Microprocessor
- Risc
- JavaScript
- Lex
Featured work
RISC Pipelined Microprocessor
Computer Architecture and Organization class project (ICOM4215) - Fall 2020
- Verilog
- Arm
- Computer Architecture
- Microprocessor
- Risc
by Valerie Otero
RISC Pipelined CPU RAM
Computer Architecture and Organization class project (ICOM4215) - Fall 2020
- Verilog
- Arm
- Computer Architecture
- Cpu
- Microprocessor
by Valerie Otero
Minesweeper
Advanced Programming class project (ICOM4015) - Spring 2018
- Java
by Valerie Otero
Megaman
Advanced Programming class project (ICOM4015) - Spring 2018
- Java
by Valerie Otero
Poker Memory
Advanced Programming class project (ICOM4015) - Fall 2017
- Java
by Valerie Otero
VirtualWorldDiscovery
Software Engineering class project (ICOM 4009) - Spring 2020
- Java
by Valerie Otero