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A. Ortiz

Full-Stack Engineer

// puerto rico, pr · UTC-4

Computer Science and Engineering undergrad at the University of Puerto Rico - Mayaguez.

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profile sourced from GitHub

Scouting report

CS/CompE coursework portfolio: Verilog CPU, AI, big data

assessed from open-source footprint

Staff
36signal

A CS-and-engineering undergrad at UPR Mayaguez whose public work is almost entirely academic: a SPARC V8 CPU in Verilog for Computer Architecture II, a Reversi/Othello agent for an AI class, and algorithm-design and big-data course projects. The range across Python, Verilog, Racket and Java shows genuine breadth, but the 'Staff' tag is unwarranted — the account is inactive (zero commits last year, all repos archived), stars are effectively nil, and there are no verified external contributions. A capable student archive rather than evidence of senior practice.

Authorship & open source

Solo authorwrote 100% of commits on SPARC_V8
22 merged PRs0 commits / yr

What they build

Backend47%
Data / ML39%
Frontend11%

Industry experience

  • Gaming
  • Data, ML & AI
  • Education & EdTech

Signal breakdown

Originality73
Impact22
Consistency23
Polish29
Stars

1

top repo 1

Original repos

11

21% forks

Followers

0

On GitHub

9.2 yr

Live demos

0

Activity

Quiet

100% stale

Strengths

  • Verified author — wrote 100% of commits on SPARC_V8
  • 22 merged pull requests
  • Original builder — 11 of their own repositories
  • Backend focus with Data / ML
  • Domain experience in Gaming & Data, ML & AI
  • Core stack: Python, HTML, Verilog, Racket