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Alexander J. Cintrón-Báez

Data / ML Engineer

// puerto rico, pr · UTC-4

Computer Engineer

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profile sourced from GitHub

Scouting report

Computer-engineering coursework: RISC CPU design and compilers

assessed from open-source footprint

Junior
40signal

A computer engineer whose repos reflect solid academic work — a Verilog RISC microprocessor implementing an ARM instruction subset, a Racket lexical analyzer, and Python utilities for course logistics and a Reddit overlap scraper. The microprocessor and compiler-adjacent projects are genuinely substantive low-level exercises that show breadth beyond typical web stacks. The caveats: all repos are abandoned, there were no commits in the past year, stars sit at one, and there are no external open-source contributions. Strong foundational CE/systems exposure captured in coursework, on an account that has since gone quiet.

Authorship & open source

Primary authorwrote 50% of commits on OverlapperSlapper
0 merged PRs0 commits / yr778 private contributions / yr

What they build

Backend62%
Data / ML20%
Mobile18%

Industry experience

  • Education & EdTech
  • Travel, Food & Hospitality

Signal breakdown

Originality83
Impact22
Consistency24
Polish33
Stars

1

top repo 1

Original repos

12

8% forks

Followers

5

On GitHub

9.4 yr

Live demos

0

Activity

Quiet

100% stale

Strengths

  • Verified author — wrote 50% of commits on OverlapperSlapper
  • Original builder — 12 of their own repositories
  • Backend focus with Data / ML
  • Domain experience in Education & EdTech & Travel, Food & Hospitality
  • Core stack: Java, Python, Verilog, Racket